QuartusII软件Error (12007): Top-level design entity "test2" is undefined_suh666888的博客-CSDN博客
DE0を使ったFPGAのお勉強-CQ出版トライアルシリーズ編 その1 – kamakurium
Quartus / Fehler bei der Compilation (VHDL) - Mikrocontroller.net
Quartus II Introduction Using Verilog Design
FPGA，VHDL报错Error (12007): Top-level design entity "xxx" is undefined _头大的小丸子的博客-CSDN博客
Debian9下Quartus II的安装– 想保持低调
FPGAの部屋 SOPC Builderを使ってみる２（NiosⅡのインスタンシエーション）
D flip flop in verilog - Electrical Engineering Stack Exchange
FPGA，VHDL报错Error (12007): Top-level design entity "xxx" is undefined _头大的小丸子的博客-CSDN博客
FPGA Quartus Error and Fixed: top level design entity "name" is undefined - YouTube
Quartus II Handbook Version 13.0
Quartus II Introduction Using Verilog Design
Help with Bidirectional Inputs/Outputs · Issue #394 · hneemann/Digital · GitHub
인텔 쿼터스18.1 사용법 : 네이버 블로그
인텔 쿼터스18.1 사용법 : 네이버 블로그
vhdl - Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined -
FPGAの部屋 SOPC Builderを使ってみる２（NiosⅡのインスタンシエーション）
FPGA，VHDL报错Error (12007): Top-level design entity "xxx" is undefined _头大的小丸子的博客-CSDN博客
![Infraled: [FPGA] Tutorial 2 - Relógio Digital em VHDL](http://3.bp.blogspot.com/-9KmImjfWUtA/U6ZKAkCRZzI/AAAAAAAAAZc/x2of_yISDy8/s1600/01.JPG "Infraled: [FPGA] Tutorial 2 - Relógio Digital em VHDL")
Infraled: [FPGA] Tutorial 2 - Relógio Digital em VHDL
Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined - Stack Overflow
Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined - Stack Overflow
Obtaining the MaxPlus Software: The student version of the MaxPlus II software can be obtained directly from the Altera web site
